1. Field of the Invention
The present invention relates to the field of integrated circuits; more specifically, it relates to stressing of integrated circuits utilizing level sensitive scan design (LSSD.)
2. Background of the Invention
Stress test modes are commonly used in modern synchronous integrated circuits to subject the integrated circuit to various types of tests that “stress” the circuit and are designed to cause reliability defects to fail during stress rather than later, in the field. One common stress type is called burn-in. During burn-in, the integrated circuit is subjected to high temperatures and higher than normal operational voltages in an effort to cause early drop out of the reliability defects.
LSSD is a method of testing integrated circuits wherein scan latches are placed between logic circuits. The scan latches allow a test vector to be sequenced through the logic circuits so the output vector can be compared to an expected vector to determine if there has been a fail in any of the logic circuits. During stress testing, all the scan latches and logic circuits are powered. For very large and high-speed integrated circuit dies at the leading edge of device technology (i.e. advanced transistor design), sub threshold leakage currents have become significant. In many cases, the stress standby current for a test like burn-in can exceed the current capability of the stress tester. Currents in excess of 75 amperes are routinely encountered. One alternative is to build higher current stress testers, but this is a very expensive solution, and earlier generations of stress testers would become obsolete.
A more desirable solution would be to reduce the standby current draw of the integrated circuit during stress.
Thus, there is an unmet need in the art for a high speed, leading edge technology integrated circuit design that requires lower standby current during stress test.